1. Field of the Invention
The present invention relates to semiconductor electronic integrated circuits, and, more particularly, to integrated circuits made of group III-V compound semiconductors including both field effect and bipolar devices.
2. Description of the Related Art
Improved performance as well as increased circuit flexibility is made possible by integrating both NPN and PNP bipolar transistors on the same chip. Silicon digital circuits make use of vertical NPN switching transistors as well as lateral PNP transistors for input logic, current sources and level shifting. The addition of junction field effect transistors (JFETs) with silicon bipolar transistors result in analog circuits which operate at high speeds while offering very high input impedences. The versatility of combining bipolar circuits and JFETs in an integrated circuit is well known. Further, the integration of silicon CMOS and bipolar transistors (BICMOS) to combine the density of CMOS with the high drive of bipolar has appeared in commercial products.
Historically GaAs/AlGaAs heterojunction bipolar transistors (HBT) have been fabricated using mesa technology in which the collector, base and emitter epi layers are sequentially grown during a single epitaxial deposition run. The emitter and base epi layer are selectively removed using two etch steps for making contact to the base and collector areas, respectively. These etches result in steps in the GaAs ranging in height between 0.4 and 1.0 micron for a typical mesa HBTs. See for example, K. Nagata et al, Self-Aligned AlGaAs/GaAs HBT with Low Emitter Resistance Utilizing In GaAs Cap Layer, 35 IEEE Tr.Elec.Dev. 2 (1988). Although high quality HBTs can be fabricated in this manner, the resulting mesa structure results in very severe topography, making it difficult to incorporate a multilevel metal system as required for high levels of integration.
Planar heterojunction bipolar transistors have been fabricated as elements of integrated circuits in the emitter down configuration; see for example, McLevige et al, U.S. Pat. No. 4,573,064 and L. Tran et al, GaAs/AlGaAs Heterojunction Emitter-Down Bipolar Transistors Fabricated on GaAs-on-Si Substrate, 8 IEEE Elec.Dev.Lett. 50 (1987). This avoids the mesa topography but has the drawbacks of limited NPN base doping and limited multiple device integration possibilities. The deep base implant through the collector limits the base doping resulting in a high base sheet resistance and a "flat" doping profile. An emitter up version appears in Gabriel et al, U.S. Pat. No. 4,672,414. And an integration possibility appears in copending application Ser. No. 063,554, filed Jun. 18, 1987 (L. Tran) where an N-channel JFET is integrated with the NPN. To integrate any more devices would require major changes in the epi and many additional processing steps. In addition, this technology requires all of the NPN transistors to be connected in the common emitter configuration which severely limits its applications.
Although a single epitaxial deposition run as used in the foregoing mesa HBTs and emitter-down HBTs does simplify the fabrication process, it limits the types of structures which can be integrated together on a single chip.
J. Tully, 7 IEEE Elec.Dev.Lett. 203 (1986) and J. Tully et al, 7 IEEE Elec.Dev.Lett. 615 (1986) grow an emitter epilayer onto an implanted base with Zn as the base dopant because of the high mass and low implant range. However, implanted Zn is difficult to activate at low temperatures. Raising the temperature high enough for good activation results in excessive diffusion due to the large diffusion coefficient for Zn, significantly increasing the base width and lateral dimensions and degrading the frequency response. Additionally, Tully integrates only a single type of device, the NPN HBT.